This invention relates to devices and methods for performing prioritized error-detection for integrated circuits having memory, and more particularly, to integrated circuits having configuration random access memory that is partitioned into sectors.
Programmable integrated circuits are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. Logic functions implemented on a programmable integrated circuit may be used to perform a variety of tasks that have varying degrees of criticality or importance to the overall functioning of the integrated circuit. For example, some logic functions can be responsible for the control of peripheral circuitry while other logic functions can be responsible for the supervision or orchestration of subordinate logic circuits.
Configuration random access memory (CRAM) in the programmable integrated circuit refers to memory cells designated for storing configuration data to implement user logic functions. Logical values stored in the CRAM are applied to circuits in the programmable integrated circuit that perform different functions within the device. These different functions may have respective levels of criticality. Consequently, the CRAM cells used to program these circuits may have different respective levels of criticality to the functioning of the programmable integrated circuit device.
Conventional programmable circuits scan CRAM cells for errors uniformly, checking each cell within the CRAM for errors with a common frequency or at a single rate. The number of CRAM cells that can be checked for errors is limited by the rate at which the CRAM cells can be read. The number of CRAM cells that can be read simultaneously is limited, for example, by the power delivery circuitry to the programmable integrated circuit, the amount of silicon area (or, die area) allocated to the CRAM cells and the power delivery circuitry, and/or the amount of metal interconnection layer use allocated to the CRAM cells and the power delivery circuitry. Specifically, reading a number of CRAM cells in excess of a threshold number of CRAM cells will result in voltage dips on shared power rails servicing the CRAM cells, causing the programmable integrated circuit to fall out of an acceptable or usable operating range/specification.
CRAM cells are susceptible to single event upsets (SEUs) that cause bit-flips in the CRAM cells. SEUs are sometimes referred to as “soft errors” because they are not permanent faults (or, “hard” errors) and can be reversed (by rewriting a correct value into the affected memory cell). When one or more CRAM cells experience bit-flips due to SEUs, the errors in the CRAM can become harder to detect and correct. Moreover, the longer a system takes to detect and correct a SEU, the likelihood of the error adversely affecting system operation or leading to faulty/erroneous operation of device resources increases. For this reason, it is desirable to perform error detection operations on CRAM arrays frequently.
However, in conventional CRAM arrays, the error detection frequency of any single CRAM cell is limited by the size of the array and the capabilities of the power supply used to operate the programmable integrated circuit. Specifically, conventional CRAM arrays undergo error detection in a uniform manner, with each CRAM cell being checked for errors at a common frequency. As an example, if a programmable integrated circuit has the ability to detect errors in a row of CRAM bits at a time, if it takes 100 nanoseconds (ns) to check each row, and if a CRAM array has 100,000 rows, then each bit in the CRAM array will be checked every 10 million ns or 10 milliseconds (ms) in a conventional arrangement.
In certain applications, however, an error in CRAM cells that configure critical logic functions that persists for over 5 ms, 2 ms, or even 1 ms may result in unacceptable performance degradation or even failure.
Therefore, improved methods for providing error detection capabilities to integrated circuits with arrays of memory cells are required.